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» Improvement of ASIC Design Processes
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ISCA
2007
IEEE
117views Hardware» more  ISCA 2007»
14 years 3 months ago
ReCycle: : pipeline adaptation to tolerate process variation
Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by t...
Abhishek Tiwari, Smruti R. Sarangi, Josep Torrella...
HOTI
2005
IEEE
14 years 2 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
DSOM
2008
Springer
13 years 10 months ago
SYMIAN: A Simulation Tool for the Optimization of the IT Incident Management Process
Incident Management is the process through which IT support organizations manage to restore normal service operation after a service disruption. The complexity of IT support organi...
Claudio Bartolini, Cesare Stefanelli, Mauro Torton...
CASES
2009
ACM
14 years 25 days ago
Exploiting residue number system for power-efficient digital signal processing in embedded processors
2's complement number system imposes a fundamental limitation on the power and performance of arithmetic circuits, due to the fundamental need of cross-datapath carry propaga...
Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shr...
SOCC
2008
IEEE
169views Education» more  SOCC 2008»
14 years 3 months ago
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...