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» Improvement of ASIC Design Processes
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DSN
2007
IEEE
14 years 3 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
ICCV
2009
IEEE
15 years 1 months ago
Evaluating Information Contributions of Bottom-up and Top-down Processes
This paper presents a method to quantitatively evaluate information contributions of individual bottom-up and topdown computing processes in object recognition. Our objective is...
Xiong Yang, Tianfu Wu, Song-Chun Zhu
DEBS
2009
ACM
14 years 3 months ago
Distributed complex event processing with query rewriting
The nature of data in enterprises and on the Internet is changing. Data used to be stored in a database first and queried later. Today timely processing of new data, represented ...
Nicholas Poul Schultz-Møller, Matteo Miglia...
ISCAS
2006
IEEE
162views Hardware» more  ISCAS 2006»
14 years 2 months ago
Combined image signal processing for CMOS image sensors
This paper presents an efficient image signal processing structure for CMOS image sensors to achieve low area and power consumption. Although CMOS image sensors (CISs) have variou...
Kimo Kim, In-Cheol Park
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
14 years 2 months ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov