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CAV
2005
Springer
127views Hardware» more  CAV 2005»
14 years 3 months ago
Incremental and Complete Bounded Model Checking for Full PLTL
Bounded model checking is an efficient method for finding bugs in system designs. The major drawback of the basic method is that it cannot prove properties, only disprove them. R...
Keijo Heljanko, Tommi A. Junttila, Timo Latvala
MTV
2003
IEEE
154views Hardware» more  MTV 2003»
14 years 3 months ago
Tuning the VSIDS Decision Heuristic for Bounded Model Checking
Bounded Model Checking (BMC) techniques have been used for formal hardware verification, with the help of tools such as GRASP (Generic search Algorithm for Satisfiability Proble...
Ohad Shacham, Emmanuel Zarpas
ECBS
2010
IEEE
209views Hardware» more  ECBS 2010»
14 years 2 months ago
Continuous Verification of Large Embedded Software Using SMT-Based Bounded Model Checking
The complexity of software in embedded systems has increased significantly over the last years so that software verification now plays an important role in ensuring the overall pr...
Lucas Cordeiro, Bernd Fischer 0002, João Ma...
ADHOCNOW
2008
Springer
13 years 11 months ago
A Lower Bound on the Capacity of Wireless Ad Hoc Networks with Cooperating Nodes
In this paper, we consider the effects on network capacity when the nodes of an ad hoc network are allowed to cooperate. These results are then compared to the theoretical upper b...
Anthony S. Acampora, Louisa Pui Sum Ip
GLVLSI
2000
IEEE
104views VLSI» more  GLVLSI 2000»
14 years 2 months ago
A new technique for estimating lower bounds on latency for high level synthesis
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
Helvio P. Peixoto, Margarida F. Jacome