37 search results - page 5 / 8 » Improving Execution Speed of FPGA using Dynamically Reconfig... |
148
Voted
CDES
2006
15 years 5 months ago
2006
As the speed gap between CPU and I/O is getting wider and wider, I/O latency plays a more important role to the overall system performance than it used to be. Prefetching consecut...
144
Voted
CODES
2007
IEEE
15 years 10 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
149
Voted
PLDI
1994
ACM
15 years 7 months ago
1994
ACM
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
130
Voted
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
— BLAST is a very popular Computational Biology algorithm. Since it is computationally expensive it is a natural target for acceleration research, and many reconfigurable archite...
140
Voted
CF
2005
ACM
15 years 5 months ago
2005
ACM
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over micro...