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» Improving IEEE 802.11 power saving mechanism
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HOTI
2011
IEEE
12 years 8 months ago
iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture
Abstract—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power cons...
Dominic DiTomaso, Avinash Kodi, Savas Kaya, David ...
ISPASS
2010
IEEE
14 years 3 months ago
Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor
After many years of prefetching research, most commercially available systems support only two types of prefetching: software-directed prefetching and hardware-based prefetchers u...
Harold W. Cain, Priya Nagpurkar
DATE
2006
IEEE
66views Hardware» more  DATE 2006»
14 years 2 months ago
Power/performance hardware optimization for synchronization intensive applications in MPSoCs
This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future powerefficient system...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
ICMCS
2006
IEEE
137views Multimedia» more  ICMCS 2006»
14 years 2 months ago
An Efficient Reference Frame Storage Scheme for H.264 HDTV Decoder
This paper proposes an efficient reference frame storage scheme for HDTV VLSI decoder to reduce external memory bandwidth requirement. The proposed scheme consists of the pixel du...
Peng Zhang, Wen Gao, Di Wu, Don Xie
IEEEPACT
2000
IEEE
14 years 1 months ago
Exploring Sub-Block Value Reuse for Superscalar Processors
The performance potential of a value reuse mechanism depends on its reuse detection time, the number of reuse opportunities, and the amount of work saved by skipping each reuse un...
Jian Huang, David J. Lilja