2032 search results - page 32 / 407 » Improving Java performance using hardware translation |
113
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ISCA
2006
IEEE
15 years 8 months ago
2006
IEEE
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encrypt...
DATE
2007
IEEE
15 years 8 months ago
2007
IEEE
We introduce a new non-intrusive on-chip cache-tuning hardware module capable of accurately predicting the best configuration of a configurable cache for an executing application....
118
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NAACL
2010
15 years 9 days ago
2010
Hierarchical phrase-based translation (Hiero, (Chiang, 2005)) provides an attractive framework within which both short- and longdistance reorderings can be addressed consistently ...
113
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PPL
2008
15 years 2 months ago
2008
The latency of broadcast/reduction operations has a significant impact on the performance of SIMD processors. This is especially true for associative programs, which make extensiv...
119
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ICS
1999
Tsinghua U.
15 years 6 months ago
1999
Tsinghua U.
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...