68 search results - page 12 / 14 » Improving Memory Subsystem Performance Using ViVA: Virtual V... |
ISCC
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—This paper presents a novel scalable switching architecture for input queued switches with its proper arbitration algorithms. In contrast to traditional switching archit...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
The Distributed Shared Memory (DSM) model is designed to leverage the ease of programming of the shared memory paradigm, while enabling the highperformance by expressing locality ...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
In P2P systems, large volumes of data are declustered naturally across a large number of peers. But it is very difficult to control the initial data distribution because every use...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
SIGGRAPH
1999
ACM
13 years 12 months ago
1999
ACM
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...