Sciweavers

131 search results - page 18 / 27
» Improving Parallel Execution Time of Sorting on Heterogeneou...
Sort
View
ICCAD
2005
IEEE
131views Hardware» more  ICCAD 2005»
14 years 5 months ago
Code restructuring for improving cache performance of MPSoCs
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
Guilin Chen, Mahmut T. Kandemir
PVM
2007
Springer
14 years 2 months ago
Optimization of Collective Communications in HeteroMPI
Abstract. HeteroMPI is an extension of MPI designed for high performance computing on heterogeneous networks of computers. The recent new feature of HeteroMPI is the optimized vers...
Alexey L. Lastovetsky, Maureen O'Flynn, Vladimir R...
PDP
2010
IEEE
14 years 11 days ago
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
Antonio Flores, Juan L. Aragón, Manuel E. A...
SC
2000
ACM
14 years 12 days ago
Real-Time Biomechanical Simulation of Volumetric Brain Deformation for Image Guided Neurosurgery
We aimed to study the performance of a parallel implementation of an intraoperative nonrigid registration algorithm that accurately simulates the biomechanical properties of the b...
Simon K. Warfield, Matthieu Ferrant, Xavier Gallez...
PPOPP
2005
ACM
14 years 1 months ago
Using multiple energy gears in MPI programs on a power-scalable cluster
Recently, system architects have built low-power, high-performance clusters, such as Green Destiny. The idea behind these clusters is to improve the energy efficiency of nodes. H...
Vincent W. Freeh, David K. Lowenthal