52 search results - page 11 / 11 » Improving Parallel Write by Node-Level Request Scheduling |
ICS
2003
Tsinghua U.
14 years 19 days ago
2003
Tsinghua U.
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an ...