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ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
12 years 11 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
HPCA
2007
IEEE
14 years 7 months ago
A Burst Scheduling Access Reordering Mechanism
Utilizing the nonuniform latencies of SDRAM devices, access reordering mechanisms alter the sequence of main memory access streams to reduce the observed access latency. Using a r...
Jun Shao, Brian T. Davis
USENIX
2007
13 years 9 months ago
Evaluating Block-level Optimization Through the IO Path
This paper focuses on evaluation of the effectiveness of optimization at various layers of the IO path, such as the file system, the device driver scheduler, and the disk drive i...
Alma Riska, James Larkby-Lahet, Erik Riedel
FAST
2010
13 years 9 months ago
Efficient Object Storage Journaling in a Distributed Parallel File System
Journaling is a widely used technique to increase file system robustness against metadata and/or data corruptions. While the overhead of journaling can be masked by the page cache...
Sarp Oral, Feiyi Wang, David Dillow, Galen M. Ship...
MASCOTS
2008
13 years 9 months ago
Modelling and Validation of Response Times in Zoned RAID
We present and validate an enhanced analytical queueing network model of zoned RAID. The model focuses on RAID levels 01 and 5, and yields the distribution of I/O request response...
Abigail S. Lebrecht, Nicholas J. Dingle, William J...