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» Improving Performance by Branch Reordering
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IEEEPACT
2006
IEEE
14 years 2 months ago
Prematerialization: reducing register pressure for free
Modern compiler transformations that eliminate redundant computations or reorder instructions, such as partial redundancy elimination and instruction scheduling, are very effectiv...
Ivan D. Baev, Richard E. Hank, David H. Gross
CORR
2009
Springer
114views Education» more  CORR 2009»
13 years 6 months ago
Distributed Branching Bisimulation Minimization by Inductive Signatures
We present a new distributed algorithm for state space minimization modulo branching bisimulation. Like its predecessor it uses signatures for refinement, but the refinement proce...
Stefan Blom, Jaco van de Pol
ASPLOS
2008
ACM
13 years 10 months ago
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
Indirect jump instructions are used to implement increasinglycommon programming constructs such as virtual function calls, switch-case statements, jump tables, and interface calls...
José A. Joao, Onur Mutlu, Hyesoon Kim, Rish...
MICRO
1999
IEEE
104views Hardware» more  MICRO 1999»
14 years 1 months ago
Control Independence in Trace Processors
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...
Eric Rotenberg, James E. Smith
MICRO
1995
IEEE
125views Hardware» more  MICRO 1995»
14 years 8 days ago
Disjoint eager execution: an optimal form of speculative execution
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible using the techniques described herein. Traditional speculative code execution is t...
Augustus K. Uht, Vijay Sindagi, Kelley Hall