328 search results - page 15 / 66 » Improving Performance of Small On-Chip Instruction Caches |
HIPEAC
2007
Springer
14 years 1 months ago
2007
Springer
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
DSD
2008
IEEE
13 years 9 months ago
2008
IEEE
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay techniques. We discovered that a filter cache, traditionally used for reducing...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the perfo...
ASPLOS
1991
ACM
13 years 11 months ago
1991
ACM
Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchies. Instead of operating on entire rows or columns of an array, blocked algorith...