Reducing Leakage through Filter Cache

We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay techniques. We discovered that a filter cache, traditionally used for reducing active power, can help reduce also leakage. The key idea is to reduce the lifetime of the lines that are in high-power state inside a leakage-saving cache. Power consumption has become one of the main concerns for designers, together with the performance. Caches account for the largest fraction of on-chip transistors in most modern processors. Therefore, they are a primary candidate for attacking the problem of the leakage. In average with the proposed solution, for instruction cache 24% improvement in leakage savings

• Type: Conference
• Year: 2008
• Where: DSD
• Authors: Roberto Giorgi, Paolo Bennati
• Keywords: Data Cache, DSD 2008, Filter Cache, Hardware, Leakage Reduction