Sciweavers

328 search results - page 20 / 66
» Improving Performance of Small On-Chip Instruction Caches
Sort
View
ISCA
2000
IEEE
93views Hardware» more  ISCA 2000»
13 years 11 months ago
Reconfigurable caches and their application to media processing
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...
SIGCOMM
1997
ACM
13 years 11 months ago
Small Forwarding Tables for Fast Routing Lookups
For some time, the networking communityhas assumed that it is impossible to do IP routing lookups in software fast enough to support gigabit speeds. IP routing lookups must nd th...
Mikael Degermark, Andrej Brodnik, Svante Carlsson,...
MICRO
1997
IEEE
139views Hardware» more  MICRO 1997»
13 years 11 months ago
The Filter Cache: An Energy Efficient Memory Structure
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
Johnson Kin, Munish Gupta, William H. Mangione-Smi...
ISPASS
2010
IEEE
14 years 2 months ago
Cache contention and application performance prediction for multi-core systems
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
Chi Xu, Xi Chen, Robert P. Dick, Zhuoqing Morley M...
ASPLOS
1998
ACM
13 years 12 months ago
Cache-Conscious Data Placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Brad Calder, Chandra Krintz, Simmi John, Todd M. A...