328 search results - page 21 / 66 » Improving Performance of Small On-Chip Instruction Caches |
ICPP
1999
IEEE
13 years 12 months ago
1999
IEEE
On-line transaction processing exhibits poor memory behavior in high-end multiprocessor servers because of complex sharing patterns and substantial interaction between the databas...
ECOOP
1995
Springer
13 years 11 months ago
1995
Springer
Previous studies have shown that object-oriented programs have different execution characteristics than procedural programs, and that special object-oriented hardware can improve p...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
ISCA
2002
IEEE
14 years 16 days ago
2002
IEEE
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...