328 search results - page 27 / 66 » Improving Performance of Small On-Chip Instruction Caches |
DEEC
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we study the use of semantic information to improve performance of transparent query caching for dynamic content web sites. We observe that in dynamic content web a...
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free...
CASES
2010
ACM
13 years 5 months ago
2010
ACM
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
TVLSI
2010
13 years 2 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
SIGMETRICS
1994
ACM
13 years 11 months ago
1994
ACM
Shade is an instruction-set simulator and custom trace generator. Application programs are executed and traced under the control of a user-supplied trace analyzer. To reduce commu...