Sciweavers

328 search results - page 28 / 66
» Improving Performance of Small On-Chip Instruction Caches
Sort
View
CGO
2004
IEEE
13 years 11 months ago
Static Identification of Delinquent Loads
The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applic...
Vlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong
ICCD
2006
IEEE
97views Hardware» more  ICCD 2006»
14 years 4 months ago
Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Sa...
ISCA
2002
IEEE
159views Hardware» more  ISCA 2002»
14 years 16 days ago
Avoiding Initialization Misses to the Heap
This paper investigates a class of main memory accesses (invalid memory traffic) that can be eliminated altogether. Invalid memory traffic is real data traffic that transfers inva...
Jarrod A. Lewis, Mikko H. Lipasti, Bryan Black
ASPLOS
1992
ACM
13 years 11 months ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta
IPCCC
1999
IEEE
13 years 12 months ago
Management policies for non-volatile write caches
Many computer hardware and software architectures buffer data in memory to improve system performance. Volatile disk or file caches are sometimes used to delay the propagation of ...
Theodore R. Haining, Darrell D. E. Long