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» Improving Performance of Small On-Chip Instruction Caches
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ACISICIS
2005
IEEE
14 years 1 months ago
An Effective Cache Overlapping Storage Structure for SMT Processors
Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle....
Liqiang He, Zhiyong Liu
BIOCOMP
2006
13 years 9 months ago
Performance of Sequence Alignment Bioinformatics Applications on General Purpose Processors: A Case Study
- Aligning specific sequences against other known sequences in a database is a central aspect of bioinformatics. New experimental data being added continuously to these databases n...
Pradeep Nair, Eugene John
EUROSYS
2011
ACM
12 years 11 months ago
SRM-buffer: an OS buffer management technique to prevent last level cache from thrashing in multicores
Buffer caches in operating systems keep active file blocks in memory to reduce disk accesses. Related studies have been focused on how to minimize buffer misses and the caused pe...
Xiaoning Ding, Kaibo Wang, Xiaodong Zhang
IEEEPACT
2005
IEEE
14 years 1 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
MICRO
2000
IEEE
80views Hardware» more  MICRO 2000»
13 years 12 months ago
Silent stores for free
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...
Kevin M. Lepak, Mikko H. Lipasti