328 search results - page 33 / 66 » Improving Performance of Small On-Chip Instruction Caches |
MICRO
2003
IEEE
14 years 26 days ago
2003
IEEE
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
OSDI
1994
ACM
13 years 9 months ago
1994
ACM
In a distributed storage system, client caches managed on the basis of small granularity objects can provide better memory utilization then page-based caches. However, object serv...
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
Trace-based compilation is a promising technique for language compilers and binary translators. It offers the potential to expand the compilation scopes that have traditionally be...
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...