328 search results - page 35 / 66 » Improving Performance of Small On-Chip Instruction Caches |
ISCA
2002
IEEE
14 years 15 days ago
2002
IEEE
Techniques for analyzing and improving memory referencing behavior continue to be important for achieving good overall program performance due to the ever-increasing performance g...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
ASPLOS
1994
ACM
13 years 11 months ago
1994
ACM
In the past decade, processor speed has become significantly faster than memory speed. Small, fast cache memories are designed to overcome this discrepancy, but they are only effe...
DASFAA
2005
IEEE
14 years 1 months ago
2005
IEEE
Peer-to-peer (P2P) computing is gaining more and more significance due to its widespread use currently and potential deployments in future applications. In this paper, we propose ...
EUROPAR
1997
Springer
13 years 11 months ago
1997
Springer
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...