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» Improving Performance of Small On-Chip Instruction Caches
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CAL
2002
13 years 7 months ago
Page-Level Behavior of Cache Contention
Cache misses in small, limited-associativity primary caches very often replace live cache blocks, given the dominance of capacity and conflict misses. Towards motivating novel cach...
Siddhartha V. Tambat, Sriram Vajapeyam
CGO
2007
IEEE
14 years 1 months ago
Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications
Run-time compilation systems are challenged with the task of translating a program’s instruction stream while maintaining low overhead. While software managed code caches are ut...
Vijay Janapa Reddi, Dan Connors, Robert Cohn, Mich...
IEEEPACT
2005
IEEE
14 years 1 months ago
Maximizing CMP Throughput with Mediocre Cores
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
John D. Davis, James Laudon, Kunle Olukotun
LCPC
2009
Springer
14 years 4 days ago
A Balanced Approach to Application Performance Tuning
Abstract. Current hardware trends place increasing pressure on programmers and tools to optimize scientific code. Numerous tools and techniques exist, but no single tool is a pana...
Souad Koliai, Stéphane Zuckerman, Emmanuel ...
ISCA
2005
IEEE
166views Hardware» more  ISCA 2005»
14 years 1 months ago
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
Emil Talpes, Diana Marculescu