328 search results - page 38 / 66 » Improving Performance of Small On-Chip Instruction Caches |
RTSS
2003
IEEE
14 years 25 days ago
2003
IEEE
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
With the growing number of programmable processing elements in today's MultiProcessor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware...
ICS
2003
Tsinghua U.
14 years 23 days ago
2003
Tsinghua U.
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
RTSS
2009
IEEE
14 years 2 months ago
2009
IEEE
—Memory accesses form an important source of timing unpredictability. Timing analysis of real-time embedded software thus requires bounding the time for memory accesses. Multipro...
SIGMETRICS
1993
ACM
13 years 11 months ago
1993
ACM
Recently there has been a surge of interest in developing performance debugging tools to help programmers tune their applications for better memory performance [2, 4, 10]. These t...