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» Improving Performance of Small On-Chip Instruction Caches
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MICRO
1999
IEEE
109views Hardware» more  MICRO 1999»
13 years 11 months ago
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
Daniel A. Connors, Wen-mei W. Hwu
SIGMOD
2009
ACM
130views Database» more  SIGMOD 2009»
14 years 7 months ago
FlashLogging: exploiting flash devices for synchronous logging performance
Synchronous transactional logging is the central mechanism for ensuring data persistency and recoverability in database systems. Unfortunately, magnetic disks are ill-suited for t...
Shimin Chen
ICS
2007
Tsinghua U.
14 years 1 months ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev
MICRO
1998
IEEE
139views Hardware» more  MICRO 1998»
13 years 11 months ago
Better Global Scheduling Using Path Profiles
Path profiles record the frequencies of execution paths through a program. Until now, the best global instruction schedulers have relied upon profile-gathered frequencies of condi...
Cliff Young, Michael D. Smith
ICS
1998
Tsinghua U.
13 years 11 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...