328 search results - page 61 / 66 » Improving Performance of Small On-Chip Instruction Caches |
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
WWW
2007
ACM
14 years 8 months ago
2007
ACM
With the explosive growth and spread of Internet, web access from mobile and rural users has become significant. But these users face problems of low bandwidth and intermittent In...
CC
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. Alias analysis, traditionally performed statically, is unsuited for a dynamic binary translator (DBT) due to incomplete control-flow information and the high complexity o...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
ASPLOS
1996
ACM
13 years 11 months ago
1996
ACM
New high-speed networks greatly encourage the use of network memory as a cache for virtual memory and file pages, thereby reducing the need for disk access. Becausepages are the f...