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» Improving Performance of Small On-Chip Instruction Caches
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MOBISYS
2009
ACM
14 years 8 months ago
Leveraging smart phones to reduce mobility footprints
Mobility footprint refers to the size, weight, and energy demand of the hardware that must be carried by a mobile user to be effective at any time and place. The ideal of a zero m...
Stephen Smaldone, Benjamin Gilbert, Nilton Bila, L...
IEEEPACT
2008
IEEE
14 years 1 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
JSA
2006
97views more  JSA 2006»
13 years 7 months ago
Dynamic feature selection for hardware prediction
It is often possible to greatly improve the performance of a hardware system via the use of predictive (speculative) techniques. For example, the performance of out-of-order micro...
Alan Fern, Robert Givan, Babak Falsafi, T. N. Vija...
WWW
2007
ACM
14 years 8 months ago
Globetp: template-based database replication for scalable web applications
Generic database replication algorithms do not scale linearly in throughput as all update, deletion and insertion (UDI) queries must be applied to every database replica. The thro...
Tobias Groothuyse, Swaminathan Sivasubramanian, Gu...
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
14 years 1 months ago
Tradeoffs in designing accelerator architectures for visual computing
Visualization, interaction, and simulation (VIS) constitute a class of applications that is growing in importance. This class includes applications such as graphics rendering, vid...
Aqeel Mahesri, Daniel R. Johnson, Neal C. Crago, S...