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DATE
2000
IEEE
90views Hardware» more  DATE 2000»
14 years 2 months ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
ISCA
1997
IEEE
104views Hardware» more  ISCA 1997»
14 years 2 months ago
Complexity-Effective Superscalar Processors
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
Subbarao Palacharla, Norman P. Jouppi, James E. Sm...
ITC
1997
IEEE
129views Hardware» more  ITC 1997»
14 years 2 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
CGF
2008
139views more  CGF 2008»
13 years 10 months ago
CHC++: Coherent Hierarchical Culling Revisited
We present a new algorithm for efficient occlusion culling using hardware occlusion queries. The algorithm significantly improves on previous techniques by making better use of te...
Oliver Mattausch, Jirí Bittner, Michael Wim...
CII
2006
141views more  CII 2006»
13 years 10 months ago
FPGA-based tool path computation: An application for shoe last machining on CNC lathes
Tool path generation is one of the most complex problems in Computer Aided Manufacturing. Although some efficient strategies have been developed, most of them are only useful for s...
Antonio Jimeno, José Luis Sánchez, H...