1045 search results - page 119 / 209 » Improving SHA-2 Hardware Implementations |
ICRA
2007
IEEE
14 years 4 months ago
2007
IEEE
— The success of sampling-based motion planners has resulted in a plethora of methods for improving planning components, such as sampling and connection strategies, local planner...
VLDB
2007
ACM
14 years 4 months ago
2007
ACM
Multi-core processors are proliferated across different domains in recent years. In this paper, we study the performance of frequent pattern mining on a modern multi-core machine....
IEEEPACT
2006
IEEE
14 years 4 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
VR
2000
IEEE
14 years 2 months ago
2000
IEEE
Due to the rapid evolution of graphics hardware, interactive 3D graphics is becoming popular on desktop personal computers. However, it remains a challenging task for a novice use...
ASPLOS
1998
ACM
14 years 2 months ago
1998
ACM
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the sup...