1045 search results - page 140 / 209 » Improving SHA-2 Hardware Implementations |
ATS
2000
IEEE
14 years 3 days ago
2000
IEEE
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
MICRO
2000
IEEE
14 years 2 days ago
2000
IEEE
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
By optimizing data layout at run-time, we can potentially enhance the performance of caches by actively creating spatial locality, facilitating prefetching, and avoiding cache con...
MICRO
1999
IEEE
13 years 12 months ago
1999
IEEE
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...
MTDT
1999
IEEE
13 years 12 months ago
1999
IEEE
The new concept of an unbalanced, hierarchicallydivided cache memory system is introduced and analyzed. This approach generalizes existing cache structures by allowing different m...