1045 search results - page 162 / 209 » Improving SHA-2 Hardware Implementations |
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Recent micro-architectural research has proposed various schemes to enhance processors with additional tags to track various properties of a program. Such a technique, which is us...
ISPASS
2008
IEEE
14 years 2 months ago
2008
IEEE
The evolution of microprocessors has been hindered by their increasing power consumption and the heat generation speed on-die. High temperature impairs the processor’s reliabili...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
SAMOS
2007
Springer
14 years 1 months ago
2007
Springer
— General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies a...
ACISICIS
2005
IEEE
14 years 1 months ago
2005
IEEE
Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle....