1045 search results - page 176 / 209 » Improving SHA-2 Hardware Implementations |
FCCM
2003
IEEE
14 years 27 days ago
2003
IEEE
Most commercial and academic floating point libraries for FPGAs provide only a small fraction of all possible floating point units. In contrast, the floating point unit generat...
IPPS
2003
IEEE
14 years 26 days ago
2003
IEEE
This paper presents a technique, called loop dissevering, to temporally partitioning any type of loop presented in programming languages. The technique can be used in the presence...
RSP
2003
IEEE
14 years 26 days ago
2003
IEEE
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
ISLPED
2003
ACM
14 years 25 days ago
2003
ACM
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
CLUSTER
2009
IEEE
14 years 9 days ago
2009
IEEE
—Achieving high-performance message passing on top of generic ETHERNET hardware suffers from the NIC interruptdriven model where coalescing is usually involved. We present an in-...