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AHS
2006
IEEE
124views Hardware» more  AHS 2006»
14 years 2 months ago
Embedded Reconfigurable Array Fabrics for Efficient Implementation of Image Compression Techniques
The discrete wavelet Transform (DWT), as defined by the Image Compression Standard JPEG-2000, is one of the most time-consuming computations which cannot be efficiently executed o...
Sajid Baloch, Tughrul Arslan, Adrian Stoica
FPL
1997
Springer
123views Hardware» more  FPL 1997»
14 years 23 days ago
P4: A platform for FPGA implementation of protocol boosters
Protocol Boosters are functional elements, inserted anddeleted fromnetwork protocol stacks on an as-neededbasis. The Protocol Booster design methodology attempts to improve end-to-...
Ilija Hadzic, Jonathan M. Smith
ISPD
2006
ACM
102views Hardware» more  ISPD 2006»
14 years 2 months ago
A faster implementation of APlace
APlace is a high quality, scalable analytical placer. This paper describes our recent efforts to improve APlace for speed and scalability. We explore various wirelength and densi...
Andrew B. Kahng, Qinke Wang
ENC
2004
IEEE
14 years 11 days ago
On the Hardware Design of an Elliptic Curve Cryptosystem
We present a hardware architecture for an Elliptic Curve Cryptography System performing the three basic cryptographic schemes: DH key generation, encryption and digital signature....
Miguel Morales-Sandoval, Claudia Feregrino Uribe
FCCM
2005
IEEE
89views VLSI» more  FCCM 2005»
14 years 2 months ago
A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration Platforms
Although researchers have presented individual techniques to efficiently utilize the Peripheral Component Interconnect (PCI) bus, their contributions fail to provide a direct path...
Petersen F. Curt, James P. Durbano, Fernando E. Or...