1045 search results - page 40 / 209 » Improving SHA-2 Hardware Implementations |
ISCA
2012
IEEE
11 years 11 months ago
2012
IEEE
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
GCB
2009
Springer
14 years 3 months ago
2009
Springer
: Solving problems in bioinformatics often needs extensive computational power. Current trends in processor architecture, especially massive multi-core processors for graphic cards...
CSREASAM
2009
13 years 9 months ago
2009
- Until recently the reasons for reduced efficiency and limited implementation of new security systems has been the insufficient performance of hardware that executes access contro...
ICCD
2001
IEEE
14 years 5 months ago
2001
IEEE
In 1987 Sedlak proposed a modulo multiplication algorithm which is suitable for smart card implementation due to it’s low latency time. It is based on ZDN (zwei_drittel_N) arith...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...