1045 search results - page 46 / 209 » Improving SHA-2 Hardware Implementations |
SC
2000
ACM
14 years 1 months ago
2000
ACM
We demonstrate that data reordering can substantially improve the performance of fine-grained irregular sharedmemory benchmarks, on both hardware and software shared-memory syste...
MICRO
1998
IEEE
14 years 29 days ago
1998
IEEE
This paper evaluates several mechanisms for repairing the return-address stack after branch mispredictions. The return-address stack is a small but important structure for achievi...
ISCA
1989
IEEE
14 years 22 days ago
1989
IEEE
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
DSD
2009
IEEE
14 years 3 months ago
2009
IEEE
—The 2D Discrete Wavelet Transform (DWT) is a time-consuming kernel in many multimedia applications such as JPEG2000 and MPEG-4. The 2D DWT consists of horizontal filtering alon...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially i...