Sciweavers

1045 search results - page 67 / 209
» Improving SHA-2 Hardware Implementations
Sort
View
HPCA
1995
IEEE
14 years 9 days ago
Software Cache Coherence for Large Scale Multiprocessors
Shared memory is an appealing abstraction for parallel programming. It must be implemented with caches in order toperform well, however, and caches require a coherence mechanism t...
Leonidas I. Kontothanassis, Michael L. Scott
INFOCOM
2012
IEEE
11 years 11 months ago
The Variable-Increment Counting Bloom Filter
—Counting Bloom Filters (CBFs) are widely used in networking device algorithms. They implement fast set representations to support membership queries with limited error, and supp...
Ori Rottenstreich, Yossi Kanizo, Isaac Keslassy
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 1 months ago
FPGA-based adaptive computing for correlated multi-stream processing
Abstract—In conventional static implementations for correlated streaming applications, computing resources may be inefficiently utilized since multiple stream processors may sup...
Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsc...
ARC
2006
Springer
201views Hardware» more  ARC 2006»
14 years 15 days ago
Dynamic Partial Reconfigurable FIR Filter Design
Abstract. This paper presents a novel partially reconfigurable FIR filter design that employs dynamic partial reconfiguration. Our scope is to implement a low-power, area-efficient...
Yeong-Jae Oh, Hanho Lee, Chong Ho Lee
FPL
2010
Springer
104views Hardware» more  FPL 2010»
13 years 6 months ago
Multiplicative Square Root Algorithms for FPGAs
Abstract--Most current square root implementations for FPGAs use a digit recurrence algorithm which is well suited to their LUT structure. However, recent computing-oriented FPGAs ...
Florent de Dinechin, Mioara Joldes, Bogdan Pasca, ...