Sciweavers

1045 search results - page 77 / 209
» Improving SHA-2 Hardware Implementations
Sort
View
AHS
2007
IEEE
252views Hardware» more  AHS 2007»
14 years 4 months ago
A Hybrid Engine for the Placement of Domain-Specific Reconfigurable Arrays
Rapid-prototyping of commercial devices and the demanding requirements for flexible hardware in mobile applications have driven the raise of reconfigurable hardware. The adaptatio...
Wing On Fung, Tughrul Arslan, Sami Khawam
ASAP
2004
IEEE
140views Hardware» more  ASAP 2004»
14 years 1 months ago
Decimal Floating-Point Division Using Newton-Raphson Iteration
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...
Liang-Kai Wang, Michael J. Schulte
IJVR
2007
202views more  IJVR 2007»
13 years 9 months ago
Full Solid Angle Panoramic Viewing by Depth Image Warping on Field Programmable Gate Array
—To construct 3D virtual scenes from two-dimensional images with depth information, image warping techniques could be used. In this paper, a novel approach of cylindrical depth i...
Xiaoying Li, Baoquan Liu, Enhua Wu
DSD
2010
IEEE
141views Hardware» more  DSD 2010»
13 years 8 months ago
Adaptive Beamforming Using the Reconfigurable MONTIUM TP
Until a decade ago, the concept of phased array beamforming was mainly implemented with mechanical or analog solutions. Today, digital hardware has become powerful enough to perfor...
Marcel D. van de Burgwal, Kenneth C. Rovers, Koen ...
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
14 years 2 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock