1045 search results - page 81 / 209 » Improving SHA-2 Hardware Implementations |
FPL
2007
Springer
14 years 4 months ago
2007
Springer
Programmable logic cores (PLCs) offer a means of providing post-fabrication re-configurability to a SoC design. Circuits implemented in a PLC will inevitably have lower timing per...
ISCA
2003
IEEE
14 years 3 months ago
2003
IEEE
Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM...
IPPS
2003
IEEE
14 years 3 months ago
2003
IEEE
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
ISCA
1993
IEEE
14 years 2 months ago
1993
IEEE
Virtual memoy page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Tratmlation L.ookaside Buffers (TLBs) do not contain a tran...
NSDI
2010
13 years 7 months ago
2010
This paper proposes to exploit physical layer information towards improved rate selection in wireless networks. While existing schemes pick good transmission rates, this paper tak...