Sciweavers

1045 search results - page 84 / 209
» Improving SHA-2 Hardware Implementations
Sort
View
ISCA
2007
IEEE
128views Hardware» more  ISCA 2007»
14 years 4 months ago
Performance and security lessons learned from virtualizing the alpha processor
Virtualization has become much more important throughout the computer industry both to improve security and to support multiple workloads on the same hardware with effective isola...
Paul A. Karger
IPPS
2002
IEEE
14 years 2 months ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...
FPL
2009
Springer
135views Hardware» more  FPL 2009»
14 years 2 months ago
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
Martin Labrecque, J. Gregory Steffan
CASES
2007
ACM
14 years 1 months ago
A self-maintained memory module supporting DMM
The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management (DMM); however, it is a challeng...
Weixing Ji, Feng Shi, Baojun Qiao
GECCO
2007
Springer
138views Optimization» more  GECCO 2007»
14 years 4 months ago
Reducing the number of transistors in digital circuits using gate-level evolutionary design
This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In ad...
Zbysek Gajda, Lukás Sekanina