1045 search results - page 86 / 209 » Improving SHA-2 Hardware Implementations |
CHES
2008
Springer
13 years 12 months ago
2008
Springer
Abstract. In this paper we present a real-world hardware-assisted attack on the wellknown A5/1 stream cipher which is (still) used to secure GSM communication in most countries all...
ASAP
2011
IEEE
2011
IEEE
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder
12 years 10 months ago
—To meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleav...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can get benefits, which improve quality and perfor...
SIGMETRICS
1994
ACM
14 years 2 months ago
1994
ACM
Shade is an instruction-set simulator and custom trace generator. Application programs are executed and traced under the control of a user-supplied trace analyzer. To reduce commu...
ICCD
2005
IEEE
14 years 6 months ago
2005
IEEE
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...