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ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
14 years 4 months ago
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmo...
MICRO
2006
IEEE
162views Hardware» more  MICRO 2006»
14 years 4 months ago
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...
Ranjith Subramanian, Yannis Smaragdakis, Gabriel H...
ACMMSP
2006
ACM
247views Hardware» more  ACMMSP 2006»
14 years 4 months ago
A flexible data to L2 cache mapping approach for future multicore processors
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cach...
Lei Jin, Hyunjin Lee, Sangyeun Cho
EUROCAST
2001
Springer
106views Hardware» more  EUROCAST 2001»
14 years 2 months ago
On CAST.FSM Computation of Hierarchical Multi-layer Networks of Automata
CAST.FSM denotes a CAST tool which has been developed at the Institute of Systems Science at the University of Linz during the years 1986-1993. The first version of CAST.FSM was i...
Michael Affenzeller, Franz Pichler, Rudolf Mittelm...
ATS
2001
IEEE
172views Hardware» more  ATS 2001»
14 years 1 months ago
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters
Testing and diagnosis are important issues in system-onchip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a buil...
Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih...