Sciweavers

1045 search results - page 94 / 209
» Improving SHA-2 Hardware Implementations
Sort
View
ICCAD
1993
IEEE
134views Hardware» more  ICCAD 1993»
14 years 2 months ago
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
In this paper, we present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, na...
Jason Cong, Yuzheng Ding
ICCD
1994
IEEE
142views Hardware» more  ICCD 1994»
14 years 2 months ago
Grammar-Based Optimization of Synthesis Scenarios
Systems for multi-level logic optimization are usually based on a set of specialized, loosely-related transformations which work on a network representation. The sequence of trans...
Andreas Kuehlmann, Lukas P. P. P. van Ginneken
CAV
2009
Springer
165views Hardware» more  CAV 2009»
14 years 2 months ago
Equivalence Checking of Static Affine Programs Using Widening to Handle Recurrences
Designers often apply manual or semi-automatic loop and data transformations on array and loop intensive programs to improve performance. The transformations should preserve the fu...
Sven Verdoolaege, Gerda Janssens, Maurice Bruynoog...
CAV
2007
Springer
108views Hardware» more  CAV 2007»
14 years 2 months ago
Parametric and Sliced Causality
Abstract. Happen-before causal partial orders have been widely used in concurrent program verification and testing. This paper presents a parametric approach to happen-before causa...
Feng Chen, Grigore Rosu
ICCAD
1998
IEEE
83views Hardware» more  ICCAD 1998»
14 years 1 months ago
Lazy transition systems: application to timing optimization of asynchronous circuits
This paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzT...
Jordi Cortadella, Michael Kishinevsky, Alex Kondra...