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EUROMICRO
1999
IEEE
13 years 11 months ago
Delft-Java Dynamic Translation
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
C. John Glossner, Stamatis Vassiliadis
FPL
2008
Springer
120views Hardware» more  FPL 2008»
13 years 9 months ago
An FPGA-based implementation of the MINRES algorithm
Due to continuous improvements in the resources available on FPGAs, it is becoming increasingly possible to accelerate floating point algorithms. The solution of a system of linea...
David Boland, George A. Constantinides
CODES
2005
IEEE
14 years 1 months ago
Iterational retiming: maximize iteration-level parallelism for nested loops
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean ...
ICIP
2007
IEEE
14 years 9 months ago
DSP Implementation of Deblocking Filter for AVS
The in-loop deblocking filter contains highly adaptive processing on both sample level and block edge level, which inevitably appears in the loop kernel of the algorithm. Therefor...
Zhigang Yang, Wen Gao, Yan Liu, Debin Zhao
ESTIMEDIA
2005
Springer
14 years 1 months ago
Custom Processor Design Using NISC: A Case-Study on DCT algorithm
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...
Bita Gorjiara, Daniel D. Gajski