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ISCAS
2003
IEEE
183views Hardware» more  ISCAS 2003»
14 years 28 days ago
Polyphase IIR filter banks for subband adaptive echo cancellation applications
Polyphase IIR structures are known to be very attractive for very high performance filters that can be designed using very few coefficients. This combined with their reduced sensi...
Artur Krukowski, Izzet Kale
MICRO
2009
IEEE
144views Hardware» more  MICRO 2009»
14 years 2 months ago
Characterizing flash memory: anomalies, observations, and applications
Despite flash memory’s promise, it suffers from many idiosyncrasies such as limited durability, data integrity problems, and asymmetry in operation granularity. As architects, ...
Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, ...
CHES
2003
Springer
146views Cryptology» more  CHES 2003»
13 years 11 months ago
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs
Abstract. Performance evaluation of the Advanced Encryption Standard candidates has led to intensive study of both hardware and software implementations. However, although plentifu...
François-Xavier Standaert, Gaël Rouvro...
MICRO
1997
IEEE
139views Hardware» more  MICRO 1997»
13 years 12 months ago
The Filter Cache: An Energy Efficient Memory Structure
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
Johnson Kin, Munish Gupta, William H. Mangione-Smi...
GECCO
2009
Springer
192views Optimization» more  GECCO 2009»
13 years 5 months ago
Improving SMT performance: an application of genetic algorithms to configure resizable caches
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
Josefa Díaz, José Ignacio Hidalgo, F...