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» Improving architecture testability with patterns
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HOTI
2008
IEEE
14 years 1 months ago
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
We present a new monolithic silicon photonics technology suited for integration with standard bulk CMOS processes, which reduces costs and improves opto-electrical coupling compar...
Christopher Batten, Ajay Joshi, Jason Orcutt, Anat...
ASAP
2007
IEEE
134views Hardware» more  ASAP 2007»
13 years 9 months ago
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
David Montgomery, Ali Akoglu
DEXA
2006
Springer
137views Database» more  DEXA 2006»
13 years 11 months ago
CLEAR: An Efficient Context and Location-Based Dynamic Replication Scheme for Mobile-P2P Networks
We propose CLEAR (Context and Location-based Efficient Allocation of Replicas), a dynamic replica allocation scheme for improving data availability in mobile ad-hoc peer-to-peer (M...
Anirban Mondal, Sanjay Kumar Madria, Masaru Kitsur...
PDIS
1991
IEEE
13 years 11 months ago
Practical Prefetching Techniques for Parallel File Systems
Improvements in the processing speed of multiprocessors are outpacing improvements in the speed of disk hardware. Parallel disk I/O subsystems have been proposed as one way to clo...
David Kotz, Carla Schlatter Ellis
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
13 years 5 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim