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» Improving architecture testability with patterns
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ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
12 years 11 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
ADBIS
1995
Springer
155views Database» more  ADBIS 1995»
13 years 11 months ago
The MaStA I/O Cost Model and its Validation Strategy
Crash recovery in database systems aims to provide an acceptable level of protection from failure at a given engineering cost. A large number of recovery mechanisms are known, and...
S. Scheuerl, Richard C. H. Connor, Ronald Morrison...
DAC
2008
ACM
14 years 8 months ago
Scan chain clustering for test power reduction
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
IPPS
2009
IEEE
14 years 2 months ago
Enabling high-performance memory migration for multithreaded applications on LINUX
As the number of cores per machine increases, memory architectures are being redesigned to avoid bus contention and sustain higher throughput needs. The emergence of Non-Uniform M...
Brice Goglin, Nathalie Furmento
DFT
2008
IEEE
120views VLSI» more  DFT 2008»
14 years 1 months ago
Built-in-Self-Diagnostics for a NoC-Based Reconfigurable IC for Dependable Beamforming Applications
Integrated circuits (IC) targeting at the streaming applications for tomorrow are becoming a fast growing market. Applications such as beamforming require mass computing capabilit...
Oscar Kuiken, Xiao Zhang, Hans G. Kerkhoff