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» Improving architecture testability with patterns
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SIGCOMM
2010
ACM
13 years 7 months ago
Cone of silence: adaptively nulling interferers in wireless networks
Dense 802.11 wireless networks present a pressing capacity challenge: users in proximity contend for limited unlicensed spectrum. Directional antennas promise increased capacity b...
Georgios Nikolaidis, Astrit Zhushi, Kyle Jamieson,...
MSWIM
2005
ACM
14 years 27 days ago
Latency-sensitive power control for wireless ad-hoc networks
We investigate the impact of power control on latency in wireless ad-hoc networks. If transmission power is increased, interference increases, thus reducing network capacity. A no...
Mohamed R. Fouad, Sonia Fahmy, Gopal Pandurangan
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 7 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
RTSS
2006
IEEE
14 years 1 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
VLDB
2004
ACM
143views Database» more  VLDB 2004»
14 years 20 days ago
Clotho: Decoupling memory page layout from storage organization
As database application performance depends on the utilization of the memory hierarchy, smart data placement plays a central role in increasing locality and in improving memory ut...
Minglong Shao, Jiri Schindler, Steven W. Schlosser...