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ICSEA
2007
IEEE
14 years 1 months ago
A Novel Framework for Test Domain Reduction using Extended Finite State Machine
Test case generation is an expensive, tedious, and errorprone process in software testing. In this paper, test case generation is accomplished using an Extended Finite State Machi...
Nutchakorn Ngamsaowaros, Peraphon Sophatsathit
CSB
2003
IEEE
14 years 24 days ago
Group Testing With DNA Chips: Generating Designs and Decoding Experiments
DNA microarrays are a valuable tool for massively parallel DNA-DNA hybridization experiments. Currently, most applications rely on the existence of sequence-specific oligonucleot...
Alexander Schliep, David C. Torney, Sven Rahmann
DAC
2007
ACM
14 years 8 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
13 years 11 months ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar
GECCO
2006
Springer
162views Optimization» more  GECCO 2006»
13 years 11 months ago
Improving evolutionary real-time testing
Embedded systems are often used in a safety-critical context, e.g. in airborne or vehicle systems. Typically, timing constraints must be satisfied so that real-time embedded syste...
Marouane Tlili, Stefan Wappler, Harmen Sthamer