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DATE
2009
IEEE
132views Hardware» more  DATE 2009»
14 years 2 months ago
Power and performance of read-write aware Hybrid Caches with non-volatile memories
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yu...
FPGA
2004
ACM
128views FPGA» more  FPGA 2004»
13 years 11 months ago
Incremental physical resynthesis for timing optimization
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...
ISMVL
2005
IEEE
108views Hardware» more  ISMVL 2005»
14 years 1 months ago
Approaching the Physical Limits of Computing
As logic device sizes shrink towards the nanometer scale, a number of important physical limits threaten to soon halt further improvements in computer performance per unit cost. H...
Michael P. Frank
ICTAC
2005
Springer
14 years 1 months ago
Stochastic Analysis of Graph Transformation Systems: A Case Study in P2P Networks
In distributed and mobile systems with volatile bandwidth and fragile connectivity, non-functional aspects like performance and reliability become more and more important. To forma...
Reiko Heckel
ASPDAC
2007
ACM
140views Hardware» more  ASPDAC 2007»
13 years 11 months ago
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
Erik Larsson, Jon Persson