68 search results - page 6 / 14 » Improving logic density through synthesis-inspired architect... |
DSN
2009
IEEE
2009
IEEE
Processor reliability enhancement through compiler-directed register file peak temperature reduction
13 years 11 months ago
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliab...
IJNSEC
2007
13 years 7 months ago
2007
The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realiza...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...