71 search results - page 7 / 15 » Improving memory bank-level parallelism in the presence of p... |
ICDCS
1996
IEEE
14 years 18 days ago
1996
IEEE
This paper evaluates the bene t of adding a shared cache to the network interface as a means of improving the performance of networked workstations con gured as a distributed shar...
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
HPCA
2012
IEEE
12 years 4 months ago
2012
IEEE
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
ICS
2007
Tsinghua U.
14 years 2 months ago
2007
Tsinghua U.
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...