Sciweavers

1001 search results - page 175 / 201
» Improving memory hierarchy performance for irregular applica...
Sort
View
ISCA
2008
IEEE
148views Hardware» more  ISCA 2008»
14 years 5 months ago
Atomic Vector Operations on Chip Multiprocessors
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Y...
ISCA
2005
IEEE
90views Hardware» more  ISCA 2005»
14 years 4 months ago
Optimizing Replication, Communication, and Capacity Allocation in CMPs
Chip multiprocessors (CMPs) substantially increase capacity pressure on the on-chip memory hierarchy while requiring fast access. Neither private nor shared caches can provide bot...
Zeshan Chishti, Michael D. Powell, T. N. Vijaykuma...
ICPP
1995
IEEE
14 years 2 months ago
Progress: A Toolkit for Interactive Program Steering
Interactive program steering permits researchers to monitor and guide their applications during runtime. Interactive steering can help make end users more effective in addressing ...
Jeffrey S. Vetter, Karsten Schwan
SECON
2008
IEEE
14 years 5 months ago
Content Distribution in VANETs Using Network Coding: The Effect of Disk I/O and Processing O/H
Abstract—Besides safe navigation (e.g., warning of approaching vehicles), car to car communications will enable a host of new applications, ranging from office-on-the-wheel supp...
Seung-Hoon Lee, Uichin Lee, Kang-Won Lee, Mario Ge...
VLDB
2004
ACM
126views Database» more  VLDB 2004»
14 years 4 months ago
STEPS towards Cache-resident Transaction Processing
Online transaction processing (OLTP) is a multibillion dollar industry with high-end database servers employing state-of-the-art processors to maximize performance. Unfortunately,...
Stavros Harizopoulos, Anastassia Ailamaki